In this role
, you will be working with various team members (Subject Matter Experts, Hardware, Software, Design team peers, and Design Verification) to understand and resolve design issues and ultimately deliver a well coded design product.
You will be expected to take your portion of the design, understand and/or update the specification, and create the RTL design from scratch or from a leveraged code block.
You may also create a standalone testbench for your design to test basic functionality before handing it off the Design Verification team for detailed testing.
You must have good communications skills, respond to queries in a timely manner, ask questions, log results in an appropriate engineering manner, and produce weekly status updates.
- Strong FPGA and/or ASIC RTL design in VHDL experience.
- Experience with Source Control Tools and Bug Tracking.
- Strong communication skills.
Xilinx Vivado Verilog or SystemVerilog Linux GIT Bug Tracking tool such as GForge or JIRA
UVM Xilinx FPGA Verification Familiar with testing VHDL source code DSP PCIE
Education / Experience
- Bachelors or Masters in Engineering from an accredited college or university experience.
- Work on independent assignments as a RTL Design Engineer.
- Must have an active secret clearance.